Digital Logic Quick Reference
Everything you need day‑to‑day – gates, Boolean algebra, circuits, and state machines.
Number Systems
Representations
- Decimal – base 10 (0‑9)
- Binary – base 2 (0‑1)
- Octal – base 8 (0‑7)
- Hexadecimal – base 16 (0‑9, A‑F)
Conversions
- Binary → Decimal: sum of powers of 2
- Decimal → Binary: repeated division by 2
- Binary → Octal: group in 3s
- Binary → Hex: group in 4s
- Octal → Binary: 3 bits per digit
- Hex → Binary: 4 bits per digit
Number Representation
| Decimal | Binary | Octal | Hex |
|---|---|---|---|
| 0 | 0000 | 0 | 0 |
| 1 | 0001 | 1 | 1 |
| 2 | 0010 | 2 | 2 |
| 3 | 0011 | 3 | 3 |
| 4 | 0100 | 4 | 4 |
| 5 | 0101 | 5 | 5 |
| 6 | 0110 | 6 | 6 |
| 7 | 0111 | 7 | 7 |
| 8 | 1000 | 10 | 8 |
| 9 | 1001 | 11 | 9 |
| 10 | 1010 | 12 | A |
| 15 | 1111 | 17 | F |
Signed Number Representations
- Sign‑Magnitude – MSB = sign, rest = magnitude
- 1's Complement – invert all bits
- 2's Complement – invert all bits + 1 (most common)
- Excess‑K – bias representation (used in floating point)
Boolean Algebra
Basic Laws
- Identity – A + 0 = A, A · 1 = A
- Null – A + 1 = 1, A · 0 = 0
- Idempotent – A + A = A, A · A = A
- Involution – (A')' = A
- Complement – A + A' = 1, A · A' = 0
- Commutative – A + B = B + A, A · B = B · A
- Associative – (A+B)+C = A+(B+C)
- Distributive – A(B+C) = AB + AC, A + BC = (A+B)(A+C)
De Morgan's Theorems
- (A + B)' = A' · B'
- (A · B)' = A' + B'
- Generalised: (A₁ + A₂ + ... + Aₙ)' = A₁' · A₂' · ... · Aₙ'
- Generalised: (A₁ · A₂ · ... · Aₙ)' = A₁' + A₂' + ... + Aₙ'
Boolean Expressions
- SOP – Sum of Products (minterms)
- POS – Product of Sums (maxterms)
- Minterm – product term where variable appears once (1 = variable, 0 = complemented)
- Maxterm – sum term where variable appears once (0 = variable, 1 = complemented)
Logic Gates
| Gate | Symbol | Operation | Truth Table |
|---|---|---|---|
| AND | & | Y = A · B | 1 if both 1 |
| OR | ≥1 | Y = A + B | 1 if either 1 |
| NOT | Δ | Y = A' | Invert |
| NAND | & with bubble | Y = (A · B)' | 0 if both 1 |
| NOR | ≥1 with bubble | Y = (A + B)' | 1 if both 0 |
| XOR | =1 | Y = A ⊕ B | 1 if different |
| XNOR | =1 with bubble | Y = (A ⊕ B)' | 1 if same |
Universal Gates
- NAND – can implement AND, OR, NOT
- NOR – can implement AND, OR, NOT
- Any digital circuit can be built using only NAND or only NOR gates
Karnaugh Maps (K‑Maps)
K‑Map Rules
- Group 1s in powers of 2 (1, 2, 4, 8, …)
- Groups must be rectangles
- Groups can wrap around edges
- Larger groups = simpler expression
- Every 1 must be in at least one group
- Don't cares (X) can be used to form larger groups
2‑Variable K‑Map
B' B
--- ---
A' | 0 | 1 |
A | 2 | 3 |
--- ---
3‑Variable K‑Map
B'C' B'C BC BC'
---- ---- ---- ----
A' | 0 | 1 | 3 | 2 |
A | 4 | 5 | 7 | 6 |
---- ---- ---- ----
4‑Variable K‑Map
C'D' C'D CD CD'
---- ---- ---- ----
A'B'| 0 | 1 | 3 | 2 |
A'B | 4 | 5 | 7 | 6 |
AB | 12 | 13 | 15 | 14 |
AB' | 8 | 9 | 11 | 10 |
---- ---- ---- ----
Don't Care Conditions (X)
- Can be treated as 0 or 1 to simplify expression
- Use X to form larger groups
- Don't care groups don't need to cover all Xs
Combinational Circuits
Basic Combinational
- Multiplexer (MUX) – selects one input based on select lines
- Demultiplexer (DEMUX) – routes input to one output
- Decoder – n inputs → 2ⁿ outputs (one active)
- Encoder – 2ⁿ inputs → n outputs
- Comparator – compares two binary numbers
- Arithmetic – adders, subtractors
Adder Circuits
- Half Adder – 2 inputs, sum + carry
- Full Adder – 3 inputs (A, B, Cin), sum + carry
- Ripple Carry Adder – cascaded full adders
- Carry Lookahead Adder – fast parallel addition
- Subtractor – using 2's complement
Multiplexer Equation
Y = I₀ · S' + I₁ · S
Full Adder Equations
Sum = A ⊕ B ⊕ Cin Carry = A·B + A·Cin + B·Cin
Decoder
n inputs → 2ⁿ outputs (one active at a time) 2×4 Decoder: 2 inputs → 4 outputs (Y₀...Y₃)
Sequential Circuits
Flip‑Flops
- SR FF – Set/Reset (S = 1, R = 1 invalid)
- JK FF – J = S, K = R (J = 1, K = 1 toggles)
- D FF – Q = D on clock edge
- T FF – Q' when T = 1 (toggles)
Triggering
- Level‑Triggered – active during clock level
- Edge‑Triggered – active on clock edge
- Positive edge – 0 → 1 transition
- Negative edge – 1 → 0 transition
- Master‑Slave – edge‑triggered (two latches)
Flip‑Flop Characteristic Equations
SR: Q⁺ = S + R'·Q (invalid: S=R=1) JK: Q⁺ = J·Q' + K'·Q D: Q⁺ = D T: Q⁺ = T ⊕ Q
Flip‑Flop Excitation Tables
| Q → Q⁺ | SR | JK | D | T |
|---|---|---|---|---|
| 0 → 0 | S=0, R=X | J=0, K=X | D=0 | T=0 |
| 0 → 1 | S=1, R=0 | J=1, K=X | D=1 | T=1 |
| 1 → 0 | S=0, R=1 | J=X, K=1 | D=0 | T=1 |
| 1 → 1 | S=X, R=0 | J=X, K=0 | D=1 | T=0 |
Registers & Counters
Registers
- Parallel Load – load all bits simultaneously
- Shift Register – shift left/right
- Serial In/Out – shift out one bit
- Universal Shift – parallel + serial
- Buffer – temporary storage
Counters
- Ripple (Asynchronous) – cascaded FFs (slow)
- Synchronous – all FFs clocked together (fast)
- Binary – count up/down
- BCD – decimal counter (0‑9)
- Ring – one hot
- Johnson – twisted ring
Finite State Machines (FSM)
FSM Types
- Moore – output depends only on current state
- Mealy – output depends on state + inputs
- Mealy has fewer states, Moore is simpler
FSM Components
- State Diagram – nodes = states, edges = transitions
- State Table – present state → next state / output
- State Encoding – assign binary values
- Transition Logic – combinational logic
FSM Design Steps
- Define problem
- Identify states and transitions
- Draw state diagram
- Create state table
- Assign binary values to states
- Derive equations (K‑maps)
- Implement with flip‑flops and gates
Memory
RAM (Random Access Memory)
- SRAM – static, fast, expensive
- DRAM – dynamic, needs refresh, cheaper
- Address bus – selects memory location
- Data bus – reads/writes data
- Read/Write control – direction
ROM (Read‑Only Memory)
- Mask ROM – factory programmed
- PROM – programmable once
- EPROM – erasable with UV
- EEPROM – electrically erasable
- Flash – block erasable
PLA & PAL
PLA (Programmable Logic Array)
- Programmable AND + OR arrays
- Can implement any Boolean function
- Flexible, but slower
PAL (Programmable Array Logic)
- Fixed OR, programmable AND
- Less flexible than PLA
- Faster and cheaper
Timing Diagrams
- Setup Time – data must be stable before clock edge
- Hold Time – data must remain stable after clock edge
- Propagation Delay – time for output to change after input
- Clock Skew – difference in clock arrival times
- Race Condition – dependent on timing
- Hazard – temporary glitch
📌 Quick Reference
Number systems: Binary (base 2), Octal (8), Hex (16)
2's complement: Invert + 1 – standard signed representation
Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
De Morgan: (A+B)' = A'·B', (A·B)' = A' + B'
K‑Map: Group 1s in powers of 2, can wrap edges, use don't cares
Flip‑Flops: SR (basic), JK (toggle), D (delay), T (toggle)
FSM: Moore (output = state), Mealy (output = state + input)
2's complement: Invert + 1 – standard signed representation
Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
De Morgan: (A+B)' = A'·B', (A·B)' = A' + B'
K‑Map: Group 1s in powers of 2, can wrap edges, use don't cares
Flip‑Flops: SR (basic), JK (toggle), D (delay), T (toggle)
FSM: Moore (output = state), Mealy (output = state + input)