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ARCHITECTURE CHEATSHEET.

A comprehensive reference for computer architecture – CPU design, pipelining, memory hierarchy, parallelism, and performance. All in one place.

REFERENCE v1.0

Computer Architecture Quick Reference

Everything you need day‑to‑day – CPU, memory, pipelines, and performance.

CPU Components

Core Components
  • ALU – Arithmetic Logic Unit (operations)
  • CU – Control Unit (decodes instructions)
  • Registers – small, fast storage (PC, IR, SP, general‑purpose)
  • Bus – data, address, control
  • Cache – small, fast memory (L1, L2, L3)
  • MMU – Memory Management Unit (virtual→physical)
Key Registers
  • PC – Program Counter (next instruction address)
  • IR – Instruction Register (current instruction)
  • SP – Stack Pointer
  • MAR – Memory Address Register
  • MDR – Memory Data Register
  • PSW – Program Status Word (flags)

Instruction Cycle

1. Fetch   – read instruction from memory (PC → MAR → memory → IR)
2. Decode  – CU decodes instruction (opcode + operands)
3. Execute – ALU performs operation (or memory access)
4. Store   – write result back to register/memory
5. Update PC – increment PC to next instruction

Instruction Formats

  • Zero‑address – stack based (push/pop)
  • One‑address – accumulator based
  • Two‑address – destination + source
  • Three‑address – two sources + destination

Pipelining

Pipeline Stages
  • 5‑stage – IF, ID, EX, MEM, WB
  • IF – Instruction Fetch
  • ID – Instruction Decode / Register Read
  • EX – Execute (ALU)
  • MEM – Memory Access
  • WB – Write Back
Pipeline Hazards
  • Structural – hardware resource conflict
  • Data – instruction depends on previous result
  • Control – branch changes flow
  • Solutions: forwarding, stalling, branch prediction

Data Hazards

  • RAW – Read After Write (true dependency)
  • WAR – Write After Read (anti‑dependency)
  • WAW – Write After Write (output dependency)
  • Forwarding – bypass result directly to next instruction
  • Stalling – insert bubbles (NOPs)

Branch Prediction

  • Static – always taken/not taken, branch history
  • Dynamic – 2‑bit predictor, BHT (Branch History Table)
  • BTB – Branch Target Buffer (predicts target address)
  • Return Address Stack – for function returns

Memory Hierarchy

Memory Levels
  • Registers – fastest, smallest (ns)
  • L1 Cache – 32‑64 KB, 1‑2 cycles
  • L2 Cache – 256‑512 KB, 5‑10 cycles
  • L3 Cache – 2‑8 MB, 15‑30 cycles
  • Main Memory (RAM) – 8‑64 GB, 100 ns
  • Secondary Storage (SSD/HDD) – slow, large
Cache Basics
  • Block / Line – unit of transfer
  • Hit – data found in cache
  • Miss – data not found (fetch from memory)
  • Hit Rate – % of accesses found in cache
  • Miss Rate – 1 – hit rate
  • Miss Penalty – time to fetch from memory
  • Average Access Time = Hit Time + Miss Rate × Miss Penalty

Cache Mapping

Mapping Description Pros Cons
Direct Mapped Block maps to exactly one cache line Simple, fast High conflict misses
Fully Associative Block can map to any line No conflict misses Expensive hardware, slower
Set‑Associative N lines per set; block maps to set Balance of conflict vs hardware More complex

Cache Write Policies

  • Write‑Through – write to cache + memory (slow, consistent)
  • Write‑Back – write only to cache (dirty bit), flush later (fast)
  • Write‑Allocate – load block on write miss
  • No‑Write‑Allocate – write directly to memory on miss

Cache Coherence (MESI Protocol)

  • M – Modified (dirty, exclusive)
  • E – Exclusive (clean, not shared)
  • S – Shared (clean, shared)
  • I – Invalid (not in cache)

Virtual Memory

Paging
  • Pages (fixed size) → Frames
  • Page Table – maps virtual → physical
  • TLB – cache for page table (fast)
  • Page Fault – page not in memory (load from disk)
  • Page Replacement – FIFO, LRU, Clock, Optimal
Segmentation
  • Variable sized segments
  • Logical view: code, data, stack
  • Segment Table – base + limit
  • Can combine with paging (segmented paging)

RISC vs CISC

Feature RISC CISC
Instruction set Simple, fixed length Complex, variable length
Instruction count More instructions per program Fewer instructions (complex operations)
Addressing modes Few (register‑based) Many (memory‑based)
Pipeline Easier to pipeline Harder to pipeline
Examples ARM, MIPS, RISC‑V x86, x86‑64
Hardware complexity Simpler (compiler does more) More complex (hardware does more)

Performance Metrics

Key Metrics
  • Clock Rate – frequency (GHz)
  • CPI – Cycles Per Instruction
  • IPC – Instructions Per Cycle (1/CPI)
  • MIPS – Millions of Instructions Per Second
  • Execution Time = (Instruction Count × CPI) / Clock Rate
  • Throughput – work done per unit time
Formulas
  • CPU Time = IC × CPI × Clock Cycle Time
  • CPU Time = IC × CPI / Clock Rate
  • Speedup = (Old Time) / (New Time)
  • Amdahl's Law: Speedup = 1 / ( (1‑f) + f/s )

Amdahl's Law

  • f = fraction of work parallelised
  • s = speedup for that fraction
  • Maximum speedup = 1 / (1‑f) (when s→∞)
  • Serial portion limits the overall speedup

Parallelism & Flynn's Taxonomy

Flynn's Taxonomy
  • SISD – Single Instruction, Single Data (traditional CPU)
  • SIMD – Single Instruction, Multiple Data (vector processors, GPUs)
  • MISD – Multiple Instruction, Single Data (rare)
  • MIMD – Multiple Instruction, Multiple Data (multi‑core)
Types of Parallelism
  • Instruction‑level – superscalar, VLIW
  • Thread‑level – multithreading (SMT, Hyper‑Threading)
  • Data‑level – SIMD, vector processing
  • Task‑level – parallel tasks (MPI, OpenMP)

Superscalar

  • Multiple instructions issued per cycle
  • Requires multiple functional units
  • Out‑of‑order execution
  • Dynamic scheduling

VLIW (Very Long Instruction Word)

  • Compiler schedules instructions in parallel
  • Wide instruction word with multiple operations
  • Hardware is simpler (no dynamic scheduling)
  • Used in DSPs, some embedded systems

Memory Organization

Byte Ordering
  • Little‑Endian – LSB first (x86)
  • Big‑Endian – MSB first (network order)
Addressing Modes
  • Immediate – operand is constant
  • Direct – operand is address
  • Indirect – operand is pointer
  • Register – operand is register
  • Register Indirect – register points to memory
  • Indexed – base + offset
📌 Quick Reference
Pipeline stages: IF, ID, EX, MEM, WB
Hazards: Structural, Data (RAW/WAR/WAW), Control
Cache mapping: Direct (simple, conflicts), Fully Associative (no conflicts, expensive), Set‑Associative (balanced)
Cache policies: Write‑Through (consistent, slower), Write‑Back (faster, dirty bit)
MESI: Modified, Exclusive, Shared, Invalid
Virtual memory: Paging (fixed), Segmentation (variable), TLB (page cache)
RISC vs CISC: Simple vs complex instructions, pipeline vs microcode
Performance: CPU Time = IC × CPI × Clock Cycle Time, Amdahl's Law: Speedup = 1 / ((1‑f) + f/s)
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